1. Field
The present disclosure relates generally to electronic circuits, and more particularly, to pseudo dual port (PDP) memories.
2. Background
Many applications require the functionality of a dual port memory, e.g., a memory capable of handling both a read and a write operation within a single clock cycle. A dual port memory typically includes two ports operating with an array of memory cells, which may be simultaneously accessed from both ports. For example, a dual port memory may access two different memory locations (addresses) in a single cycle. In order to reduce the size of the memory, a pseudo-dual port or PDP memory may be used to replace a dual port memory. The core of the PDP memory may be a single-core memory. Accordingly, the memory array of the PDP memory may allow for a single memory access at one instance and not two simultaneous memory accesses as with the dual port memory. The PDP memory may emulate the dual port memory in having two ports. In one implementation, the PDP memory may receive a clock for an access cycle and sequentially perform two memory accesses in that access cycle.